OK6410A 开发板 (八) 68 linux-5.11 OK6410A linux 内核同步机制 atomic 的实现

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解决的问题是什么

所有竞态原因

实现

32bit

// 下面为 atomic_add 的定义

arch/arm/include/asm/atomic.h

36 #define ATOMIC_OP(op, c_op, asm_op)

37 static inline void atomic_##op(int i, atomic_t *v)

38 {

39 unsigned long tmp;

40 int result;

41

42 prefetchw(&v->counter);

43 __asm__ __volatile__("@ atomic_" #op "n"

44 "1: ldrex %0, [%3]n"

45 " " #asm_op " %0, %0, %4n"

46 " strex %1, %0, [%3]n"

47 " teq %1, #0n"

48 " bne 1b"

49 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

50 : "r" (&v->counter), "Ir" (i)

51 : "cc");

52 }

...

218 #define ATOMIC_OPS(op, c_op, asm_op)

219 ATOMIC_OP(op, c_op, asm_op)

220 ATOMIC_OP_RETURN(op, c_op, asm_op)

221 ATOMIC_FETCH_OP(op, c_op, asm_op)

...

223 ATOMIC_OPS(add, +=, add)

64bit

arch/arm/include/asm/atomic.h

304 #define ATOMIC64_OP(op, op1, op2)

305 static inline void atomic64_##op(s64 i, atomic64_t *v)

306 {

307 s64 result;

308 unsigned long tmp;

309

310 prefetchw(&v->counter);

311 __asm__ __volatile__("@ atomic64_" #op "n"

312 "1: ldrexd %0, %H0, [%3]n"

313 " " #op1 " %Q0, %Q0, %Q4n"

314 " " #op2 " %R0, %R0, %R4n"

315 " strexd %1, %0, %H0, [%3]n"

316 " teq %1, #0n"

317 " bne 1b"

318 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)

319 : "r" (&v->counter), "r" (i)

320 : "cc");

321 }

1bit

arch/arm/include/asm/bitops.h

31 /*

32 * These functions are the basis of our bit ops.

33 *

34 * First, the atomic bitops. These use native endian.

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